The present invention relates to a metallization arrangement for a semiconductor structure having a first substructure plane; a second metallization plane having a first and a second adjacent interconnect; a first intermediate dielectric for mutual electrical insulation of the first substructure plane and second metallization lane; and via holes filled with a conductive material in the first intermediate dielectric for connecting the first substructure plane and second metallization plane. The invention likewise relates to a corresponding fabrication method.
The term semiconductor structure is to be understood in the general sense and can therefore encompass both single-layered and multilayered structures with any desired semiconductor components. By way of example, the semiconductor structure is an integrated circuit for which the metallization arrangement provides internal or external wiring.
FIG. 2 shows a diagrammatic illustration of a known metallization arrangement for a semiconductor structure.
In FIG. 2, 1 designates a semiconductor structure, for example an electrical circuit integrated in a silicon substrate, L1 designates a first liner layer made of silicon dioxide, M1 designates a first metallization plane, ILD designates an intermediate dielectric, V designates a via hole filled with a conductive material FM, L2 designates a second liner layer, M2 designates a second metallization layer, LBA designates a first interconnect, LBB designates a second interconnect and O designates an interspace between the first and second interconnects LBA, LBB, and K designates critical locations of the structure.
In general, the aim of introducing the intermediate dielectric ILD having a low dielectric constant is to reduce the capacitive coupling of adjacent interconnects and thus improve the functional efficiency with the chip are unchanged. However, integrating the intermediate dielectric ILD having a low dielectric constant generally requires the provision of the liner layer L1 or L2, for example in the form of a silicon oxide liner or silicon nitride liner, for patterning the via holes V and as diffusion barrier (e.g. in the case of ALCu metallization).
The relatively high dielectric constant of such a liner layer L1 or L2 in the form of a silicon oxide liner or silicon nitride liner has an adverse effect, however, on the capacitive coupling of adjacent interconnects, for example LBA and LBB. Such critical locations in the known arrangement in accordance with FIG. 2 are designated by K.